One conventional parallel processor includes a plurality of micro-engines and circuitry to load program code into program code memories in the micro-engines. In operation of this conventional parallel processor, the circuitry loads the program code into the program code memories during a boot process, executed as a result of a reset of parallel processor. After the circuitry has completed loading of the program code into the program code memories and the boot process has completed, the micro-engines may begin executing the program code loaded in the program code memories. The execution of the program code loaded in the program code memories may result in the micro-engines manipulating and/or modifying, in accordance with the program code, data transmitted to the micro-engines for processing by the micro-engines.
In this conventional parallel processor, the program code loaded in the program code memories may not be modified unless all of the micro-engines have halted execution of the program code. That is, in this conventional parallel processor, while the micro-engines are executing the program code loaded in the program codes memories, the program code loaded in the program code memories may not be modified. While the micro-engines have halted execution of this program code, the micro-engines may be unable to manipulate and/or modify data transmitted to the micro-engines for processing by the micro-engines. Additionally, the halting of execution of the program code by the micro-engines may result in corruption and/or loss of data that was in the process of being manipulated and/or modified by the micro-engines when the halting of such execution occurred.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.